Superconducting circuits are one of the leading technologies proposed for quantum computing and cryptography applications that are expected to provide significant enhancements to national security applications where communication signal integrity or computing power are needed. They are operated at temperatures <100 kelvin. Efforts on fabrication of superconducting devices have mostly been confined to university or government research labs, with little published on the mass producing of superconducting devices. Therefore, many of the methods used to fabricate superconducting devices in these laboratories utilize processes or equipment incapable of rapid, consistent fabrication. Furthermore, the need for low temperature processing currently presents one of the more significant barriers to mass production of superconducting devices.
One of the common devices employed in superconducting circuits is a Josephson junction (JJ), which can be embedded in a dielectric interconnect structure. Typically, Josephson junctions (JJs) interconnect structures are formed employing low temperature materials (e.g., formed at less than or equal to 180° C.) since the utilization of higher temperature materials can result in damage to the structure of the JJ, and thus cause deterioration of the normal operation of the JJ. The utilization of low temperature materials in the superconducting device interconnects results in more losses than the utilization of high temperature materials. Furthermore, the use of legacy processing techniques to form a JJ result in large topography problems and therefore problems with yield and reliability of the JJ. Both of these reasons lead to a minimum size of JJ of the order of 1 um diameter which limits the density and functionality of an integrated chip.
An attempt has been made to employ low loss high temperature dielectrics (e.g., formed at temperatures greater than 180° C.) in forming circuits with JJs. One example method uses a non-planarized deposition of sputtered quartz to form the high temperature dielectric. However, this process is not scalable to the desired 0.25 um technologies, and the lack of planarization limits these devices to 4 levels of interconnect.